1. Field of the Invention
The present invention is generally directed to the field of semiconductor manufacturing, and, more particularly, to a method of forming an opening in an insulating layer where a conductive contact will be formed.
2. Description of the Related Art
There is a constant drive to reduce the size, or scale, of transistors to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. A conventional integrated circuit device, such as a microprocessor, is typically comprised of millions of transistors formed above the surface of a semiconducting substrate. For the integrated circuit device to function, the transistors must be electrically connected to one another through conductive interconnections, i.e., conductive lines and plugs.
Many modern integrated circuit devices are very densely packed, i.e., there is very little space between the transistors formed above the substrate. Thus, these conductive interconnections are made in multiple layers to conserve plot space on the semiconducting substrate. This is typically accomplished through the formation of alternating layers of conductive lines and conductive plugs formed in layers of insulating materials formed on the device. As is readily apparent to those skilled in the art, the conductive plugs are means by which various layers of conductive lines, and/or semiconductor devices, may be electrically coupled to one another. In the industry, conductive plugs that are in contact with portions of the underlying integrated circuit device, e.g., the source/drain regions of a transistor, are known as xe2x80x9ccontactsxe2x80x9d. Conductive plugs that connect conductive lines are known as xe2x80x9cviasxe2x80x9d. The conductive lines and plugs may be made from a variety of conductive materials, such as copper, aluminum, aluminum alloys, titanium, tantalum, titanium nitride, tantalum nitride, tungsten, etc.
A typical prior art process flow for forming an illustrative conductive contact will now be described. As shown in FIG. 1A, a plurality of transistors 20, separated by a trench isolation region 22, are formed above a semiconducting substrate 10. Each transistor 20 is comprised of a gate insulation layer 12, a gate electrode 14, a sidewall spacer 16, and a plurality of source/drain regions 18. The transistors 20 may be comprised of a variety of known materials, and they may be fabricated using a variety of known processing techniques. For example, the gate insulation layer 12 may be comprised of silicon dioxide, etc. Similarly, the gate electrode 14 may be comprised of a variety of materials such as a doped polycrystalline silicon (polysilicon). The sidewall spacer 16 may also be comprised of a variety of materials, such as, silicon dioxide, silicon nitride, silicon oxynitride, etc. The source/drain regions 18 may be formed by performing one or more ion implantation processes.
After formation of the transistors 20, a layer 24, sometimes referred to as a bottom anti-reflective coating (BARC) layer, is formed above the transistors 20 and a surface 11 of the semiconducting substrate 10. In connection with the fabrication of modem semiconductor devices, the layer 24 is typically comprised of a deposited layer of silicon nitride, silicon oxynitride, etc., that may have a thickness ranging from approximately 300-800xc3x85. Thereafter, an insulating layer 26 is formed above the layer 24. The insulating layer 26 may be comprised of a variety of materials, such as silicon dioxide, silicon dioxide doped with boron or phosphorous, etc. The insulating layer 26 may have a thickness ranging from approximately 4000-7000xc3x85. Next, an antireflective coating layer (ARC) 28 is then formed above the insulating layer 26. This ARC layer 28 may be formed from a variety of materials using a variety of known processing techniques. For example, the ARC layer 28 may be comprised of silicon nitride, silicon oxynitride, etc., that may have a thickness ranging from approximately 200-800xc3x85.
Eventually, using multiple lithographic patterning and etching processes, an opening will be formed through the ARC layer 28, the insulating layer 26, and the layer 24, so that a conductive contact may be formed therein to establish electrical connection with one of the source/drain regions 18 of the transistor 20. However, such an opening must be properly aligned with the underlying transistor 20 so that it may serve its intended function. For example, if the opening was so misaligned that it was positioned over the trench isolation region 22, then the conductive contact formed therein would not serve its intended function. Fortunately, in modern semiconductor fabrication facilities such gross misalignment problems are uncommon. However, given the very small spacing between transistors in modern devices and the difficulties with patterning such small features across a large silicon wafer, misalignment of the opening for the conductive contact occurs with resulting adverse consequences to device performance.
Figure 1B depicts a problem encountered in forming openings in an insulating layer for conductive contacts when there is a misalignment error. As shown therein, the opening 29 is formed in the ARC layer 28 using a patterned layer of a photoresist (not shown) as a mask. Thereafter, an etching process is performed to define the opening 29 in the insulating layer 26. During this process, it is intended that the layer 24 act as an etch stop layer with respect to the etching of the opening 29 in the insulating layer 26. Thereafter, another etching process is used to remove the portion of the layer 24 positioned beneath the opening 29 defined in the insulating layer 26.
However, in situations where the opening 29 is misaligned with respect to the transistor 20, as depicted in FIG. 1B, problems may arise when using the aforementioned prior art etching scheme and integration. In particular, although the layer 24 is designed to be an etch stop layer with respect to the etching of the opening 29 in the insulating layer 26, in practice some or all of the layer 24 may be consumed during this process. That is, the etching process used to form the opening 29 through the insulating layer 26 may, in fact, consume some or all of the layer 24 and the sidewalls spacer 16 positioned adjacent the gate electrode 14, as indicated in FIG. 1B.
In such situations, device performance may be impaired, in that leakage currents may be increased and/or short circuit paths may be established between the gate electrode 14 and the source/drain region 18. Thus, while it is desirable to avoid misalignment of the contact opening 29 with respect to the underlying transistor 20, is also desirable to have a contact etch scheme that solves, or at least reduces, some or all of the aforementioned problems when misalignment of the contact opening 29 does occur.
The present invention is directed to a method that solves, or at least reduces, some or all of the aforementioned problems.
The present invention is directed to a method of forming a conductive contact on an integrated circuit device. In one illustrative embodiment, the method comprises forming a transistor above a semiconducting substrate, and forming a first layer comprised of an orthosilicate glass (OSG) material above the transistor and the substrate. The method further comprises forming a second layer comprised of an insulating material above the first layer, and performing at least one etching process to define an opening in the second layer for a conductive contact to be formed therein, wherein the first layer comprised of an orthosilicate glass material acts as an etch stop layer during the etching of the opening in the second layer. In another illustrative embodiment, the method further comprises forming a third layer comprised of an orthosilicate glass material above the insulating layer prior to forming the opening in the insulating layer, and performing at least one etching process to define an opening in the first layer and to remove substantially all of the third layer from above the insulating layer.
In another aspect, the present invention is directed to an integrated circuit device comprised a plurality of transistors formed above a semiconducting substrate, and an etch stop layer comprised of an orthosilicate glass material positioned above the transistors and the substrate. The device further comprises a layer of insulating material positioned above the etch stop layer, and a conductive contract positioned in an opening formed in the insulating layer and in the etch stop layer.